STA Engineer
Tags: “STA Synthesis”
Role:
mustHaveSkills: [“STA Synthesis”]

STA Engineer
Tags: “STA Synthesis”
Role:
mustHaveSkills: [“STA Synthesis”]

STA Engineer
Tags: “STA Synthesis”
Role:
mustHaveSkills: [“STA Synthesis”]

STA Engineer
Tags: “STA Synthesis”
Role:
mustHaveSkills: [“STA Synthesis”]

STA Engineer
Tags: “STA Synthesis”
Role:
mustHaveSkills: [“STA Synthesis”]

STA Engineer
Tags: “STA Synthesis”
Role:
mustHaveSkills: [“STA Synthesis”]

STA Engineer
Tags: “STA Synthesis”
Role:
mustHaveSkills: [“STA Synthesis”]

STA/Synthesis Engineer
Tags: STA, Synthesis, ASIC Synthesis, Primetime
Role:
mustHaveSkills: [STA, Synthesis, ASIC Synthesis, Primetime]

STA/Synthesis Engineer
Tags: STA, Synthesis, ASIC Synthesis, Primetime
Role:
mustHaveSkills: [STA, Synthesis, ASIC Synthesis, Primetime]

STA/Synthesis Engineer
Tags: STA, Synthesis, ASIC Synthesis, Primetime
Role:
mustHaveSkills: [STA, Synthesis, ASIC Synthesis, Primetime]

Requirement Details - Must have Worked on 45nm.Experience on Synthesis. -Experience on STA -Should have worked on Synthesis using RTL complier -Should have worked on STA using Gold Time -Should be good at Flow and methodology. -Networking domain Knowledge is an added advantage -Working knowledge...
Tags: STA, Synthesis, Design Compiler, Primetime, Goldtime, Primetime, Goldtime, Primetime, Goldtime
Role: STA/Synthesis Engineer
mustHaveSkills: [STA, Synthesis, Design Compiler, Primetime, Goldtime, Primetime, Goldtime]

STA/Synthesis Engineer
Tags: STA, Synthesis, ASIC Synthesis, Primetime
Role:
mustHaveSkills: [STA, Synthesis, ASIC Synthesis, Primetime]

STA/Synthesis Engineer
Tags: STA, Synthesis, ASIC Synthesis, Primetime
Role:
mustHaveSkills: [STA, Synthesis, ASIC Synthesis, Primetime]

STA/Synthesis Engineer
Tags: STA, Synthesis, ASIC Synthesis, Primetime
Role:
mustHaveSkills: [STA, Synthesis, ASIC Synthesis, Primetime]

Static Timing Analysis, Synthesis, Formal Verification, Synopsys Flow, RTL Coding, LEC, DC/Primetime, Spyglass, Synthesis of IP's, Timing Analysis
Tags: Static Timing Analysis, Synthesis, Formal Verification, Synopsys Flow, RTL Coding , LEC, DC/Primetime, Spyglass, Synthesis of IP's, Timing Analysis, Spyglass, Synthesis of IP's, Timing Analysis, Spyglass, Synthesis of IP's, Timing Analysis
Role: STA Engineer
mustHaveSkills: [Static Timing Analysis, Synthesis, Formal Verification, Synopsys Flow, RTL Coding , LEC, DC/Primetime, Spyglass, Synthesis of IP's, Timing Analysis, Spyglass, Synthesis of IP's, Timing Analysis]

Job Description:- Role: Logic Design Job Location : Pune Years of Experience : 5 to 12 Years Education : BE/B.Tech/ME/M.Tech/MS Candidates interested in this opportunity can send the resume to  saku@ vlsijobs.net
Tags: "Verilog"/VHDL, "Logic Design", RTL, RTL Design, "ASIC Design", "Digital Design", ASIC Architecture Design, "Logic Design", RTL, RTL Design, "ASIC Design", "Digital Design", ASIC Architecture Design
Role: ASIC Design Engineer/ASIC Architecture Design Engineer
mustHaveSkills: ["Verilog"/VHDL, "Logic Design", RTL, RTL Design, "ASIC Design", "Digital Design", ASIC Architecture Design]

URGENT!! Looking For Professionals with Good Experience in Library/cell Characterization and Timing Closure with Scripting Skills ~ This position is required in the team which is responsible for delivering Standard Cell IP for High-performance processor design. High frequency designs require a...
Tags: library characterization, timing closure, scripting skills, cell characterization, Static timing analysis, Perl, Tcl, cell characterization, Static timing analysis, Perl, Tcl, cell characterization, Static timing analysis, Perl, Tcl
Role: Library Characterization and timing Professionals
mustHaveSkills: [library characterization, timing closure, scripting skills, cell characterization, Static timing analysis, Perl, Tcl, cell characterization, Static timing analysis, Perl, Tcl]

We have very good openings for ASIC Design top most product based MNC in Bangalore. If you interested for please send me your updated to srinadh.cambio@gmail.com Experience: 5+   And also we have openings for Layer2/Layer3 Dev/Testing, Packet forwarding, Security (Developing/Testing), and...
Tags: 'ASIC Design', RTL, Verilog, VHDL, Layer2/Layer3, Ethernet, Layer2/Layer3, Ethernet, Layer2/Layer3, Ethernet
Role: Software Developer
mustHaveSkills: ['ASIC Design', RTL, Verilog, VHDL, Layer2/Layer3, Ethernet, Layer2/Layer3, Ethernet]

We have very good openings for ASIC Design top most product based MNC in Bangalore. If you interested for please send me your updated to swapna@cambio.co.in Experience: 5+   And also we have openings for Layer2/Layer3 Dev/Testing, Packet forwarding, Security (Developing/Testing), and Storage...
Tags: 'ASIC Design', RTL, Verilog, VHDL
Role: Software Developer
mustHaveSkills: ['ASIC Design', RTL, Verilog, VHDL]

We have very good openings for ASIC Design top most product based MNC in Bangalore. If you interested for please send me your updated to srinadh.cambio@gmail.com Experience: 5+   And also we have openings for Layer2/Layer3 Dev/Testing, Packet forwarding, Security (Developing/Testing), and...
Tags: 'ASIC Design', RTL, Verilog, VHDL, Layer2/Layer3, Ethernet, Layer2/Layer3, Ethernet, Layer2/Layer3, Ethernet
Role: Software Developer
mustHaveSkills: ['ASIC Design', RTL, Verilog, VHDL, Layer2/Layer3, Ethernet, Layer2/Layer3, Ethernet]