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Anand S Moghe Head/VP/GM-R&D, eINfochips Ltd.
 
Anand S Moghe's Profile
Anand S Moghe
Head/VP/GM-R&D, eINfochips Ltd.
eINfochips Ltd.
confidential
confidential
Ahmedabad, India
Toostep 
Professional summary
Anand S Moghe's Experience
Current :

Head/VP/GM-R&D, eINfochips Ltd.
Hardware
India, Ahmedabad

Working from 2007

Previous :

Infochips Ltd.
Ahmedabad

Worked from 2007 to 2009

Brief summary :

Experience Chronicle Head, ASIC Design and Backend Services, eInfochips Ltd., Ahmedabad, Jul 2007 - Jan 2009

Previous :

Infochips Ltd
Ahmedabad

Worked from 2007 to 2009

Brief summary :

HEAD, ASIC Design and Backend services, eInfochips Ltd, Ahmedabad Jul 2007 - Jan 2009 Responsiblilities: Heading and managing a team of 90 members engaged in design (front end and backend) and verification services for the execution of multi-site projects and reporting to the CEO. Actively involved in the process of Business Development by converting business opportunities into executed business. Associated with the processes improvement program in the organisation. Entrusted with the task of enhancing ASIC front end and analog design skills. Mentoring and Coaching next level staff. Charged with the Resource management, recruitment and SoC verification project. Managing resources and placing the right resources at the right time for the projects, while keeping a healthy number of spare resources. Liaison and interacting with the customers on a regular basis. Responsible for imparting technical training to engineers on a regular basis. Achievements: Successfully executed verification and design services business to the tune of 4.5M USD. Applauded by the management for improving the level of training in design for the fresh recruits and introducing new EDA tools into the division.

Previous :

VP Engineering Qualcore Logic Ltd.

Worked from 2006 to 2007

Brief summary :

VP, Engineering, Qualcore Logic Ltd., May 2006 - Jun 2007

Previous :

ENGINEERING Qualcore Logic Ltd.
Hyderabad

Worked from 2006 to 2007

Brief summary :

VP- ENGINEERING, Qualcore Logic Ltd., Hyderabad May 2006 - Jun 2007 Responsibilities: Leading a team of 120 to manage entire engineering activity in Qualcore Logic in USA and India for ASIC development, Project execution and products developed. Reporting to the Managing Director. Tasked with managing the development of semiconductor IPs, execution of inhouse/ customer Projects and Resource Management. Key person for defining the organizational structure, improving processes, defining engineering practices, staffing, development of a training program for new recruits and ensuring growth of the company in terms of numbers and engineering skills. Providing leadership to various project groups and help them complete the projects by acting as a mentor and facilitator. DIRECTOR, IC ENGINEERING, Nuelight India Semiconductors. Sep 2005 - Apr 2006 Responsibilities: Managing India operations of IC design for Nuelight USA with a team consisting of 11 engineers for RTL development, verification and IP integration. Responsible for overall coordination between the USA and India engineering operations for the NOVA project. Actively involved in the third party IP integration, RTL development, synthesis and Board level testing involving DDR SDRAM, RISC processor, WISHBONE protocol, interconnect switch, flash memory etc.

Previous :

IC Engineering Nuelight Semiconductors Pvt Ltd.
India

Worked from 2005 to 2006

Brief summary :

Director of IC Engineering, Nuelight India Semiconductors Pvt Ltd., Sep 2005-Apr 2006

Previous :

Sr. Engineering Manager, Mentor Graphics Pvt Ltd.
India

Worked from 2002 to 2005

Brief summary :

Sr. Engineering Manager, Mentor Graphics India Pvt Ltd., Apr 2002 - Aug 2005

Previous :

SR ENGINEERING MANAGER, , Mentor Graphics India ,
Hyderabad

Worked from 2002 to 2005

Brief summary :

SR ENGINEERING MANAGER, Mentor Graphics India, Hyderabad Apr 2002 - Aug 2005 Responsibilities: Assigned responsibility of managing the group for DFT tools validation, development of semiconductor IPs and Engineering Resource management. Instrumental in starting an IP development group for Mentor Graphics in Hyderabad. Achievements: Successfully led the team in the development of EHCI host controller (USB 2.0) which was proven on STRATIX-II FPGA under Windows drivers. Applauded for providing an elegant way of computing CRC of 16-bit (or 32-bit) data to the EHCI design team. Responsible for taking a third party IP (USB OHCI controller) and modifying it to make it meet the Mentor Graphics standards for Verilog coding and design practices. Individual contribution also included the design and verification of a RISC Processor PIC 16c67 (semiconductor IP).

Previous :

QUALCORE LOGIC LTD

Worked from 1997 to 2002

Brief summary :

QUALCORE LOGIC LTD. Jan 1997 - Mar 2002 DIRECTOR (PROJECTS) Entrusted with the task of resource allocation, schedules, negotiation and people management for all the ongoing Projects. Attending management committee (MC) meetings and representing to MC the engineers problems, discussing solutions to these, discussing wages and wage structure for the company. One of the contributors to the verification and design guidelines document that was followed in Qualcore. MANAGER - TURNKEY PROJECT (BIU development for C-Cubes CL9600 set-top box controller chip) Responsibilities: Managing and motivating a team of about 20 engineers, one Project Lead and two senior members of technical staff. Liaison and coordination with the customer, intiating meetings, negotiating and tracking schedules. Achievements: Successfully designed the JTAG module in BIU project.The BIU was capable of interfacing to PowerPC bus, 68000 bus, PCI bus, C-Cubes proprietary memory and control bus. The BIU, besides interfacing to these processor and memory buses, had a multi-channel DMA controller, JTAG controller and an ATA interface. This chip has been successfully taped out by C-Cube. Individual contribution in other projects for C-Cube includes implementing a fractional-N Digital PLL, a Leaky integrator, a digital AGC module, etc. MANAGER - DEVELOPMENT Supervised the development of Processor IP cores - 8051XA (Philips), 68HC11, 6805, 6808, (Motorola), mcs251, mcs151 (Intel) and h8/300 (Hitachi). Developed a uniform design methodolgy applicable to the development of many Processor / microcontroller IP cores. Responsible for the Verilog design/verification of major blocks of the mcs251, and the interrupt control block, the address prefetch block etc. Designed the CPU of a RISC processor h8/300. Provided guidance to the team for implementing the control structure of the microprocessors. Trained the development team in using good design and coding standards. Worked on improving the OpenMORE rating for the IP cores. Followed the design Re-use methodology in developing new cores and revamped the legacy cores to make them adhere to Desgn Re-use standards. Planning and forming the advertisement for recruitment, setting question papers, conducting technical interviews and training the recruits in Industry practices in digital design and Verilog RTL. Actively involved in lecturing on Digital Systems and Verilog HDL at VEDA-IIT, a VLSI training institute of Qualcore Logic Ltd. Involved in framing the course structure for Advanced Diploma in VLSI design and also for the M.S. course in VLSI Engineering being offered by VEDA - IIT (Hyd) in association with JNTU, Hyderabad. DEVELOPMENT CONSULTANT / ENGG. MANAGER., CMC Ltd., Hyderabad Aug 1983 - Dec 1996 Responsibilities: Assigned responsibility of handling Design and development and Project management Actively involved in Porting of UNIX from PDP-11 on to a 32-bit 68000 based machine, developing a fault tolerant uP board using TMR principle and development and production of a 24-Mflop vector processor. Pl refer to ANNEXURE `A for projects handled. Achievements: Won creativity award for usage of the IBM PC in CLASS project of CMC. The class project had a nation -wide reach. Selected as the manager for the Compass offshore development team for EDA utilities (1995).

Previous :

Qualcore Logic Ltd

Worked from 1997 to 2002

Brief summary :

Director (Projects), Qualcore Logic Ltd, Jan 1997 - Mar 2002

Previous :

Senior Manager, CMC Ltd.

Worked from 1983 to 1996

Brief summary :

Senior Manager (Compass Development Group), CMC Ltd., Aug 1983 - Dec 1996

Previous :

TECHNICAL OFFICER, ECIL

Worked from 1976 to 1981

Brief summary :

TECHNICAL OFFICER, ECIL Jul 1976 - Dec 1981 Managed defense projects with a team of 6 Engineers in the area of medium power RF transmitters and receivers. Designed high-SFDR (Spurious Free Dynamic Range) receivers and medium power VHF power amplifiers, transmitters, Antenna Tuning Units (ATU) for transforming the antenna impedance to a standard resistive value. Experienced the idiosynchracies of RF devices/ Equipment and 4th order Butterworth and Chebyshev Filters.

Previous :

ECIL

Worked from 1976 to 1981

Brief summary :

Technical officer, ECIL, Jul 1976 - Dec 1981

 
 
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