Required 7 Software Developer for Thomson Digital at Chennai For more information dial 044-22251141
Tags: Software Developer
Role: Software Developer
mustHaveSkills: [Software Developer]

hands on experience with multiple tape-outs should have thorough knowledge of flooplan, clock tree implementation, P R, low-power He should know Cadence, Mentor and/or Synopsys tools for above skills. Person should be able to independently execute functional as well as timing ECOs on the design.
Tags: multiple tape-outs, Cadence, SOC projects
Role: Back end Designer
mustHaveSkills: [multiple tape-outs, Cadence, SOC projects ]

Digital IP design [Specification to RTL to Digital Flow till Synthesis and post silicon support]
Tags: Digital Designer, Digital IP design, Timing Analysis
Role: Digital Designer
mustHaveSkills: [Digital Designer, Digital IP design, Timing Analysis]

Responsible for Design Support of digital part of the PHY SubSystem for High Speed Serial Link, i.e., usb2, Ethernet, with Controller, Bus adaptor etc.
Tags: RTL , Digital Designer
Role: Digital Designer
mustHaveSkills: [RTL , Digital Designer]

Hands on experience with multiple tape-outs: Person should have thorough knowledge of flooplan, clock tree implementation, P R, low-power design implementation techniques, IR drop analysis, Sign-off Timing analysis and physical verification. He should know Cadence, Mentor and/or Synopsys tools...
Tags: Backend, IR Drop, P &R, Floorplan, Floorplan, Floorplan
Role: Backend Design
mustHaveSkills: [Backend, IR Drop, P &R, Floorplan, Floorplan]

Design Support of digital part of the PHY SubSystem for High Speed Serial Link, i.e., usb2, Ethernet, with Controller, Bus adaptor etc.
Tags: Ethernet,, Synthesys tools, RTL design
Role: Digital Designer
mustHaveSkills: [Ethernet,, Synthesys tools, RTL design ]

Strong fundamentals of MOS based circuit design. Sound fundamentals  in analog/mixed-signal circuit design.  Hands-on experience Exposure in some/all of the following areas -  Op-Amps , Regulators, Current Voltage References, Sense-Amplifier, Mixed Signal design – Memory Blocks, Charge-pump,...
Tags: Non-Volatile Memory design , SPICE simulators, Digital-Analog blocks
Role: Non-Volatile Memory design
mustHaveSkills: [Non-Volatile Memory design , SPICE simulators, Digital-Analog blocks ]

Design Support of digital part of the PHY SubSystem for High Speed Serial Link, i.e., usb2, Ethernet, with Controller, Bus adaptor etc.
Tags: RTL design , SubSystem, digital Simulation
Role: Digital Designer
mustHaveSkills: [RTL design , SubSystem, digital Simulation]

Experience in flooplan, clock tree implementation, P R, low-power design implementation techniques, IR drop analysis, Sign-off Timing analysis and physical verification. Knowledge of Cadence, Mentor and/or Synopsys tools for above skills. Person should be able to independently execute functional...
Tags: flooplan, , clock tree implementation, low-power design
Role: Digital Designer (Back End)
mustHaveSkills: [flooplan, , clock tree implementation, low-power design ]

Understanding of basic ASIC design flow. Person should be self starter and willing to learn new tools/flows using  various CAD flows/ tools from vendors.  
Tags: SOC integration, Synthesis,CAD flows , TA, Encounter.
Role: FE Flow position
mustHaveSkills: [SOC integration, Synthesis,CAD flows , TA, Encounter.]

Person should be able to independently execute functional as well as timing ECOs on the design. He should have worked on atleast couple of  40nm and beyond technology node tape-outs. Person very strong in technical reporting and willing to excel his/her career in technical domains participating...
Tags: Synthesis, design constraints, , Formality, Hand-off, DFT insertion , trenta and/or Cadence tools
Role: Front End
mustHaveSkills: [Synthesis, design constraints, , Formality, Hand-off, DFT insertion , trenta and/or Cadence tools ]

He should have worked on atleast couple of  40nm and beyond technology node tape-outs. Person very strong in technical reporting and willing to excel his/her career in technical domains participatingin challenging and strong deadline driven multi-domain SOC projects on latest technology.
Tags: Synthesis, design constraints, 40nm , timing analysis., Formality, Hand-off, DFT insertion
Role: Front End
mustHaveSkills: [Synthesis, design constraints, 40nm , timing analysis., Formality, Hand-off, DFT insertion ]

Person should be self starter and willing to learn new tools/flows using  various CAD flows/ tools from vendors.
Tags: SOC integration, Synthesis, TA, Encounter., TCL, PERL and/or JAVA , ASIC design
Role: Front End Flow
mustHaveSkills: [SOC integration, Synthesis, TA, Encounter., TCL, PERL and/or JAVA , ASIC design ]

Person should be able to independently execute functional as well as timing ECOs on the design. He should have worked on atleast couple of 40nm and beyond technology node tape-outs. Person very strong in technical reporting and willing to excel his/her career in technical domains participating...
Tags: Back End ,flooplan, clock tree implementation,40nm , Cadence, Mentor
Role: Back End
mustHaveSkills: [Back End ,flooplan, clock tree implementation,40nm , Cadence, Mentor ]

Design Support of digital part of the PHY SubSystem for High Speed Serial Link, i.e., usb2, Ethernet, with Controller, Bus adaptor etc.
Tags: Synthesys tools., digital Simulation, Verifications,, RTL design
Role: Subsystem
mustHaveSkills: [Synthesys tools., digital Simulation, Verifications,, RTL design]

#Understanding of key SRAM blocks  #Knowledgeable in design rule analysis, parasitic extraction, noise crosstalk issues, yield improvement and manufacturability issues and design for test principles  
Tags: Memory Layout, Layout Tiling, SRAM blocks ,CMOS fundamentals
Role: Memory Layout
mustHaveSkills: [Memory Layout, Layout Tiling, SRAM blocks ,CMOS fundamentals]

Responsible for Design Support of digital part of the PHY SubSystem for High Speed Serial Link, i.e., usb2, Ethernet, with Controller, Bus adaptor etc.
Tags: RTL, Digital Design
Role: Digital Designer
mustHaveSkills: [RTL, Digital Design]

Responsibilities • Create digital surface models and capture design intent from Design Sketches, concept themes and scan data. • Should provide alternative proposals and Capture Design Intent creatively • Deliver production quality surfaces and ensures surface meet Clients Global Design Standards...
Tags: Alias, Surface Modeling, ICEM Surf
Role: Digital Sculpting
mustHaveSkills: [Alias, Surface Modeling, ICEM Surf]

Responsibilities • Create digital surface models and capture design intent from Design Sketches, concept themes and scan data. • Should provide alternative proposals and Capture Design Intent creatively • Deliver production quality surfaces and ensures surface meet Clients Global Design Standards...
Tags: Alias, Surface Modeling, ICEM Surf
Role: Digital Sculpting
mustHaveSkills: [Alias, Surface Modeling, ICEM Surf]

Required 1 Accounts Manager forJOHARI DIGITAL HEALTHCARE at Jodhpur For more information dial 9351789472
Tags: Accounts Manager
Role: Accounts Manager
mustHaveSkills: [Accounts Manager]