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Started by : Vivek Acharya, Project Manager, Royal Philips Electronics   10 06 2008 10:01:19 +0000
Industry : SemiconductorFunctional Area : R&D(Operations)
Activity:  101 views;  last activity : 07 06 2010 20:18:09 +0000

Hi friends,

Please provide your valuable inputs.... 

 
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1 2 3 4 5
1 Analyze & Optimize Power
2 Requirement based sizing of silicon
3 Asynchronous Crore
4 clock gating and multiple voltage thresholds
5 Shutting power to an unused block
6 power on all peripherals only when they are required.

Analyze & Optimize Power

idea posted by Vivek Acharya Project Manager, Royal Philips Electronics
My take is to analyze and optimize power in everything from clock trees to I/Os. Have a balanced approach to power optimization that spans the entire RTL-to-GDS flow, and ensure that high-power areas in a design are identified and that steps to reduce power consumption are automated.....
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The current design based on clock frequency has reached its peak. It is time to think for alternative. Some of the intel chips consume 150A at 1.5V at maximum performance. These chips can serve as a room heaters in a cold climate

V.Kadal Amutham

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Requirement based sizing of silicon

idea posted by srikanth nerella Firmware Engineer, Motorola

generally the power optimization is a tradeoff with space & performance, if you want one need to sacrifice other.

so it is better to customize your product based on it's usage & need.

Like some components in the entire IC may be used rarely (for some intializations & configurations etc) so these components can be reduced in size(will increase power consumption) and other for components, the power can be optimized by increasing size on tradeoff basis.

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Asynchronous Crore

idea posted by Kadal Amutham Head R&D , Fifth Generation Technologies (P) Ltd

Thinking is going on to switch over design to asynchronous from synchronous design. Asynch. design consume 1/3 power for the same processing 

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clock gating and multiple voltage thresholds

idea posted by Rakesh Deshmukh Project Lead, Texas Instrument

clock gating and multiple voltage thresholds are well-established and supported by existing tools.To save leakage, some designs use power gating to shut down blocks that aren't in use, using multiple-threshold CMOS (MTCMOS) switches. The power-down and power-on sequences can be extremely complex to design and verify.But it will work in its best way

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Shutting power to an unused block

idea posted by Devena Mohite Project Lead, Microchip Technology
Selective shutting power down to an unused block will help but one needs to be careful when choosing which blocks to shut down and when, because powering up a block & shutting down also consumes power so it should be optimized properly...
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power on all peripherals only when they are required.

idea posted by venugopal Senior firmware developer, nvidia

If all peripherals and clocks are switched on only when they are needed, I hope power consumptions will be the least.

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