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Cadence or Synopsys or Magma tools Jobs
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PNR opening with Product Based MNC (Semiconductor Domain) @ Greater Noida.
The incubent will be responsible for Physical Implementation of Imaging SoC"s. Primarily - BE (Floor Plan, PNR, Clock-tree, TA, IRdrop, Sign-ff, Mask finishing) and participate in FE (synthèses, TA, Formal Verification, Sign-off, Hand-off)
Updated:
2012-Mar-08 07:32 PM
By: Roland and AssociatesIndustry: SemiconductorRole: PNR
Experience Level: 1.0 to 2.0 yrsLocation: Greater Noida (India)
Opening for PNR with Product Based MNC Semiconductor @ Greater Noida.
The incubent will be responsible for Physical Implementation of Imaging SoC"s. Primarily - BE (Floor Plan, PNR, Clock-tree, TA, IRdrop, Sign-ff, Mask finishing) and participate in FE (synthèses, TA, Formal Verification, Sign-off, Hand-off)
Updated:
2012-Mar-08 07:32 PM
By: Roland and AssociatesIndustry: SemiconductorRole: PNR
Experience Level: 1.0 to 2.0 yrsLocation: Greater Noida (India)
Magma Talus Jobs
Job Title : Magma Talus Engineer Experience : 1 - 15 Job Location : Bangalore, Ahmedabad, Pune, Chennai, Hyderabad Position exist at all levels. Skills : Physical Design, ASIC Backend, SOC encounter, Magma Talus, IC Compiler, floor planning, PnR, Placement and routing, synthesis and STA, Static...
Updated:
2012-Mar-08 07:32 PM
By: Roland and AssociatesIndustry: SemiconductorRole: Magma Talus Engineer
Experience Level: 1.0 to 15.0 yrsLocation: Hyderabad (India)
Magma Talus Jobs
Job Title : Magma Talus Engineer Experience : 1 - 15 Job Location : Bangalore, Ahmedabad, Pune, Chennai, Hyderabad Position exist at all levels. Skills : Physical Design, ASIC Backend, SOC encounter, Magma Talus, IC Compiler, floor planning, PnR, Placement and routing, synthesis and STA, Static...
Updated:
2012-Mar-08 07:32 PM
By: Roland and AssociatesIndustry: SemiconductorRole: Magma Talus Engineer
Experience Level: 1.0 to 15.0 yrsLocation: Hyderabad (India)
Synopsys ICC Jobs
Job Title : Synopsys ICC Engineer Experience : 1 - 15 Job Location : Bangalore, Ahmedabad, Pune, Chennai, Hyderabad Position exist at all levels. Skills : Physical Design, ASIC Backend, SOC encounter, Magma Talus, IC Compiler, floor planning, PnR, Placement and routing, synthesis and STA, Static...
Updated:
2012-Mar-08 07:32 PM
By: Roland and AssociatesIndustry: SemiconductorRole: Synopsys ICC Engineer
Experience Level: 1.0 to 15.0 yrsLocation: Chennai (India)
Synopsys ICC Jobs
Job Title : Synopsys ICC Engineer Experience : 1 - 15 Job Location : Bangalore, Ahmedabad, Pune, Chennai, Hyderabad Position exist at all levels. Skills : Physical Design, ASIC Backend, SOC encounter, Magma Talus, IC Compiler, floor planning, PnR, Placement and routing, synthesis and STA, Static...
Updated:
2012-Mar-08 07:32 PM
By: Roland and AssociatesIndustry: SemiconductorRole: Synopsys ICC Engineer
Experience Level: 1.0 to 15.0 yrsLocation: Chennai (India)
Synopsys Certify Jobs in Pune
Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...
Updated:
2012-Apr-16 10:38 AM
By: Roland and AssociatesIndustry: SemiconductorsRole: Synopsys Certify Designer
Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)
Synopsys Certify Jobs in Pune
Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...
Updated:
2012-Apr-16 10:38 AM
By: Roland and AssociatesIndustry: SemiconductorsRole: Synopsys Certify Designer
Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)
Synopsys Certify Jobs in Pune
Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...
Updated:
2012-Apr-16 10:38 AM
By: Roland and AssociatesIndustry: SemiconductorsRole: Synopsys Certify Designer
Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)
Synopsys Certify Jobs in Pune
Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...
Updated:
2012-Apr-16 10:38 AM
By: Roland and AssociatesIndustry: SemiconductorsRole: Synopsys Certify Designer
Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)
Synopsys Certify Jobs in Pune
Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...
Updated:
2012-Apr-16 10:38 AM
By: Roland and AssociatesIndustry: SemiconductorsRole: Synopsys Certify Designer
Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)
Synopsys Certify Jobs in Pune
Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...
Updated:
2012-Apr-16 10:38 AM
By: Roland and AssociatesIndustry: SemiconductorsRole: Synopsys Certify Designer
Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)
Synopsys Certify Jobs in Pune
Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...
Updated:
2012-Mar-20 12:19 PM
By: Roland and AssociatesIndustry: SemiconductorsRole: Synopsys Certify Designer
Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)
Cadence Encounter Jobs
Job Title : Cadence Encounter Engineer Experience : 1 - 15 Job Location : Bangalore, Ahmedabad, Hyderabad Pune, Chennai Position exist at all levels. Skills : Physical Design, ASIC Backend, SOC encounter, Magma Talus, IC Compiler, floor planning, PnR, Placement and routing, synthesis and STA,...
Updated:
2012-Mar-08 07:32 PM
By: Roland and AssociatesIndustry: SemiconductorRole: Cadence Encounter Engineer
Experience Level: 1.0 to 15.0 yrsLocation: Ahmedabad (India)
Cadence Encounter Jobs
Job Title : Cadence Encounter Engineer Experience : 1 - 15 Job Location : Bangalore, Ahmedabad, Hyderabad Pune, Chennai Position exist at all levels. Skills : Physical Design, ASIC Backend, SOC encounter, Magma Talus, IC Compiler, floor planning, PnR, Placement and routing, synthesis and STA,...
Updated:
2012-Mar-08 07:32 PM
By: Roland and AssociatesIndustry: SemiconductorRole: Cadence Encounter Engineer
Experience Level: 1.0 to 15.0 yrsLocation: Ahmedabad (India)
Cadence Encounter Jobs
Job Title : Cadence Encounter Engineer Experience : 1 - 15 Job Location : Bangalore, Ahmedabad, Hyderabad Pune, Chennai Position exist at all levels. Skills : Physical Design, ASIC Backend, SOC encounter, Magma Talus, IC Compiler, floor planning, PnR, Placement and routing, synthesis and STA,...
Updated:
2012-Mar-08 07:32 PM
By: Roland and AssociatesIndustry: SemiconductorRole: Cadence Encounter Engineer
Experience Level: 1.0 to 15.0 yrsLocation: Ahmedabad (India)
Physical Design, RTL Design, DFT, Design For Testability, ASIC Backend, SOC encounter, Magma Talus, IC Compiler, floor planning, PnR, Placement and routing, Physical Design Professionals, San Jose San Diego
Verification Professionals Jobs JD Positions : Physical Design Professionals Experience: 3 -8 Years Location : San Jose / San Deigo (US) Skills :synthesis and STA, Static timing analysis,Synopsys ICC, ASIC Implementation, P&R, Cadence encounter, RTL to GDS, RTL to GDSII. Mail your CV to...
Updated:
2012-Mar-29 12:31 PM
By: Roland and AssociatesIndustry: SemiconductorRole: Physical Design Professionals
Experience Level: 3.0 to 8.0 yrsLocation: San Jose San Diego (US)
USA Jobs for Magma Talus Experts
USA Jobs for Magma Talus Experts
Updated:
2012-May-27 01:21 PM
By: Roland and AssociatesIndustry: SemiconductorRole: Physical Design
Experience Level: 4.5 to 8.0 yrsLocation: USA
USA Jobs for Magma Talus Users
USA Jobs for Magma Talus Users
Updated:
2012-May-27 01:21 PM
By: Roland and AssociatesIndustry: SemiconductorRole: Physical Design
Experience Level: 4.5 to 8.0 yrsLocation: USA
Floor Planning, IR Drop Analysis, P&R, Physical Design Engineer, A Leading Services Company, Bangalore,Hyderabad,Vizag,Noida
We are looking "Physical Design Engineer/Lead/Manager" with 2-15Yrs,share profile to shalini@fusionservices.in and call us on 8951434706.
Updated:
2012-May-14 11:55 AM
By: Fusion Intellect ServicesIndustry: IT Services, SemiconductorRole: Physical Design Engineer
Experience Level: 2.0 to 15.0 yrsLocation: Bangalore ,Hyderabad ,Vizag,Noida (India)
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