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Cisco Jobs

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Jobs in Bangalore for Circuit Design Engg

B.E/B-Tech in electronics engineering with years of relevant experience or MS/M-Tech degree in electronics/VLSI with Experience of high speed custom circuit design. Knowledge of bias generation, on-chip regulation, on-chip impedance circuits,PLL. Experience in designing DDR2/3 or PCIe1/2, SATA,...

Updated: 2013-May-20 12:12 PM

By: Cambio ConsultingIndustry: SemiconductorRole: Circuit Design Engineer

Experience Level: 3.0 to 10.0 yrsLocation: Bangalore (India)

Keywords: DDR PLL SATA XAUI On-chip regulation SATA XAUI On-chip regulation SATA XAUI On-chip regulation

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Jobs in Bangalore for Platform Developers

Hi Good day!! This is let you know regarding the openings in Bangalore with the top based MNC`s. Please find the JD below. Qualifications - Typically requires BE or equivalent Job Description: The individual will play the role of individual contributor in a development role in the Global...

Updated: 2013-May-20 12:10 PM

By: Cambio ConsultingIndustry: Communications and NetworkingRole: Platform Developers@ Bangalore

Experience Level: 6.0 to 20.0 yrsLocation: Bangalore Hyd Chennai (India)

Keywords: BSP 'Boot Loader' Device Driver uboot "kernel programming" "Board Support Package" "linux internals" "Linux kernel" Device Driver uboot "kernel programming" "Board Support Package" "linux internals" "Linux kernel" Device Driver uboot "kernel programming" "Board Support Package" "linux internals" "Linux kernel"

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Jobs on Asic Physical Design @ Bangalore

Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning

Updated: 2013-May-20 12:08 PM

By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer

Experience Level: 4.0 to 15.0 yrsLocation: Bangalore (India)

Keywords: Floorplan Place & Route Placement Netlist to GDS Implementation Multimillion gate Soc Designs Flipchip designs TCL/Perl/Shell Tapeouts Synthesis Clock Distribution Extraction Timing Closure Partitioning Integration Signoff Clock Distribution Extraction Timing Closure Partitioning Integration Signoff Clock Distribution Extraction Timing Closure Partitioning Integration Signoff

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Jobs for UI Developer @ Noida

Web Developer Working knowledge of Unix/Linux and Apache. Experience in building web pages using HTML, CSS, Javascript, Jquery etc. Experience with XML and XML-related APIs. In depth knowledge of software engineering and object-oriented programming principles. Knowledge of software engineering...

Updated: 2013-May-18 10:58 AM

By: Cambio ConsultingIndustry: IT ServicesRole: Web Developer

Experience Level: 3.0 to 6.0 yrsLocation: Noida (India)

Keywords: HTML CSS JavaScript Jquery XML XML-related APIs Software Engineering Object-Oriented Programming Principles UML Scrum Ajax Unix Linux Apache Unix Linux Apache Unix Linux Apache

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UI Developer Jobs @ Noida

Updated: 2013-May-18 10:56 AM

By: Cambio ConsultingIndustry: IT ServicesRole: Web Developer

Experience Level: 3.0 to 6.0 yrsLocation: Noida (India)

Keywords: HTML CSS JavaScript Jquery XML XML-related APIs Software Engineering Object-Oriented Programming Principles UML Scrum Ajax Unix Linux Apache Unix Linux Apache Unix Linux Apache

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Asic Physical Design jobs@ Bangalore

Updated: 2013-May-18 10:49 AM

By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer

Experience Level: 4.0 to 15.0 yrsLocation: Bangalore (India)

Keywords: Floorplan Place & Route Placement Netlist to GDS Implementation Multimillion gate Soc Designs Flipchip designs TCL/Perl/Shell Tapeouts Synthesis Clock Distribution Extraction Timing Closure Partitioning Integration Signoff Clock Distribution Extraction Timing Closure Partitioning Integration Signoff Clock Distribution Extraction Timing Closure Partitioning Integration Signoff

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Jobs on Asic Physical Design @ Bangalore

Updated: 2013-May-18 10:45 AM

By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer

Experience Level: 4.0 to 15.0 yrsLocation: Bangalore (India)

Keywords: Floorplan Place & Route Placement Netlist to GDS Implementation Multimillion gate Soc Designs Flipchip designs TCL/Perl/Shell Tapeouts Synthesis Clock Distribution Extraction Timing Closure Partitioning Integration Signoff Clock Distribution Extraction Timing Closure Partitioning Integration Signoff Clock Distribution Extraction Timing Closure Partitioning Integration Signoff

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Physical Design Openings @ Bangalore

Updated: 2013-May-18 10:43 AM

By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer

Experience Level: 4.0 to 15.0 yrsLocation: Bangalore (India)

Keywords: Floorplan Place & Route Placement Netlist to GDS Implementation Multimillion gate Soc Designs Flipchip designs TCL/Perl/Shell Tapeouts Synthesis Clock Distribution Extraction Timing Closure Partitioning Integration Signoff Clock Distribution Extraction Timing Closure Partitioning Integration Signoff Clock Distribution Extraction Timing Closure Partitioning Integration Signoff

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Physical Design Jobs @ Bangalore

Updated: 2013-May-18 10:42 AM

By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer

Experience Level: 4.0 to 15.0 yrsLocation: Bangalore (India)

Keywords: Floorplan Place & Route Placement Netlist to GDS Implementation Multimillion gate Soc Designs Flipchip designs TCL/Perl/Shell Tapeouts Synthesis Clock Distribution Extraction Timing Closure Partitioning Integration Signoff Clock Distribution Extraction Timing Closure Partitioning Integration Signoff Clock Distribution Extraction Timing Closure Partitioning Integration Signoff

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Hirings for Physical Design Professionals @ Bangalore

Updated: 2013-May-18 10:40 AM

By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer

Experience Level: 4.0 to 15.0 yrsLocation: Bangalore (India)

Keywords: Floorplan Place & Route Placement Netlist to GDS Implementation Multimillion gate Soc Designs Flipchip designs TCL/Perl/Shell Tapeouts Synthesis Clock Distribution Extraction Timing Closure Partitioning Integration Signoff Clock Distribution Extraction Timing Closure Partitioning Integration Signoff Clock Distribution Extraction Timing Closure Partitioning Integration Signoff

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Hirings for DFT Professionals @ Bangalore

PREFERRED EXPERIENCE: - The candidate must have thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, Memory BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Experience with test tools such as FastScan and TestKompress is highly...

Updated: 2013-May-18 10:34 AM

By: Cambio ConsultingIndustry: SemiconductorRole: DFT Engineer

Experience Level: 7.0 to 8.0 yrsLocation: Bangalore (India)

Keywords: DFT Boundary Scan ATPG JTAG Coverage Analysis EDA Tools High speed/Low power designs 65nm/40nm/28nm PBIST/MBIST/LBIST Signal integrity checks STA Back end Timing Closure Post Silicon Validation ATE Debug Logic equivalence checking RTL implementation Signal integrity checks STA Back end Timing Closure Post Silicon Validation ATE Debug Logic equivalence checking RTL implementation Signal integrity checks STA Back end Timing Closure Post Silicon Validation ATE Debug Logic equivalence checking RTL implementation

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Hirings for Verification Professionals @ Bangalore

SystemVerilog, Vera, Specman, SystemC OVM/UVM exp in verification with minimum of 2 years with SV OVM assertion based verification/formal verification DDRx or LPDDRx

Updated: 2013-May-18 10:25 AM

By: Cambio ConsultingIndustry: HardwareRole: Verification Engineer

Experience Level: 6.0 to 9.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verification verilog System Verilog eRM/VMM/OVM Specman PCIe Vera ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script

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Openings for Verification Engineers @ Bangalore

SystemVerilog, Vera, Specman, SystemC OVM/UVM exp in verification with minimum of 2 years with SV OVM assertion based verification/formal verification DDRx or LPDDRx

Updated: 2013-May-18 10:15 AM

By: Cambio ConsultingIndustry: HardwareRole: Verification Engineer

Experience Level: 6.0 to 9.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verification verilog System Verilog eRM/VMM/OVM Specman PCIe Vera ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script

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Openings for Verification @ Bangalore

SystemVerilog, Vera, Specman, SystemC OVM/UVM exp in verification with minimum of 2 years with SV OVM assertion based verification/formal verification DDRx or LPDDRx

Updated: 2013-May-18 10:10 AM

By: Cambio ConsultingIndustry: HardwareRole: Verification Engineer

Experience Level: 6.0 to 9.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verification verilog System Verilog eRM/VMM/OVM Specman PCIe Vera ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script

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Openings on Verification @ Bangalore

SystemVerilog, Vera, Specman, SystemC OVM/UVM exp in verification with minimum of 2 years with SV OVM assertion based verification/formal verification DDRx or LPDDRx

Updated: 2013-May-18 10:09 AM

By: Cambio ConsultingIndustry: HardwareRole: Verification Engineer

Experience Level: 6.0 to 9.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verification verilog System Verilog eRM/VMM/OVM Specman PCIe Vera ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script

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Jobs on Verification @ Bangalore

SystemVerilog, Vera, Specman, SystemC OVM/UVM exp in verification with minimum of 2 years with SV OVM assertion based verification/formal verification DDRx or LPDDRx

Updated: 2013-May-18 10:07 AM

By: Cambio ConsultingIndustry: HardwareRole: Verification Engineer

Experience Level: 6.0 to 9.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verification verilog System Verilog eRM/VMM/OVM Specman PCIe Vera ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script

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Jobs for Verification Engineers @ Bangalore

SystemVerilog, Vera, Specman, SystemC OVM/UVM exp in verification with minimum of 2 years with SV OVM assertion based verification/formal verification DDRx or LPDDRx

Updated: 2013-May-18 10:05 AM

By: Cambio ConsultingIndustry: HardwareRole: Verification Engineer

Experience Level: 6.0 to 9.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verification verilog System Verilog eRM/VMM/OVM Specman PCIe Vera ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script

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Hirings for Verification Engineers @ Bangalore

SystemVerilog, Vera, Specman, SystemC OVM/UVM exp in verification with minimum of 2 years with SV OVM assertion based verification/formal verification DDRx or LPDDRx

Updated: 2013-May-18 10:01 AM

By: Cambio ConsultingIndustry: HardwareRole: Verification Engineer

Experience Level: 6.0 to 9.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verification verilog System Verilog eRM/VMM/OVM Specman PCIe Vera ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script ARM AHB/AXI AMBA DDR/LPDDR Perl Shell Script

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DFT Hirings at Bangalore

Updated: 2013-May-18 09:18 AM

By: Cambio ConsultingIndustry: SemiconductorRole: DFT Engineer

Experience Level: 7.0 to 8.0 yrsLocation: Bangalore (India)

Keywords: DFT Boundary Scan ATPG JTAG Coverage Analysis EDA Tools High speed/Low power designs 65nm/40nm/28nm PBIST/MBIST/LBIST Signal integrity checks STA Back end Timing Closure Post Silicon Validation ATE Debug Logic equivalence checking RTL implementation Signal integrity checks STA Back end Timing Closure Post Silicon Validation ATE Debug Logic equivalence checking RTL implementation Signal integrity checks STA Back end Timing Closure Post Silicon Validation ATE Debug Logic equivalence checking RTL implementation

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DFT Jobs, Bangalore

Updated: 2013-May-18 09:13 AM

By: Cambio ConsultingIndustry: SemiconductorRole: DFT Engineer

Experience Level: 7.0 to 8.0 yrsLocation: Bangalore (India)

Keywords: DFT Boundary Scan ATPG JTAG Coverage Analysis EDA Tools High speed/Low power designs 65nm/40nm/28nm PBIST/MBIST/LBIST Signal integrity checks STA Back end Timing Closure Post Silicon Validation ATE Debug Logic equivalence checking RTL implementation Signal integrity checks STA Back end Timing Closure Post Silicon Validation ATE Debug Logic equivalence checking RTL implementation Signal integrity checks STA Back end Timing Closure Post Silicon Validation ATE Debug Logic equivalence checking RTL implementation

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