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FPGA Jobs

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FPGA Design-Team Lead jobs @ Hyderabad

FPGA Design-Team Lead jobs @ Hyderabad

Job Description: Years of Experience: 5 to 10 years Job Location: Hyderabad ·   Experience in designing ASIC/FPGA based systems and platforms ·   Exceptional debug skills, system validation knowledge · Working knowledge with interfaces like DDR2/3, RGMII/GMII/XUAI, PCIe, SPI, I2C, etc. ·  ...
Updated:  2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: FPGA Design
Experience Level: 5.0 to 10.0 yrsLocation: Hyderabad  (India)
Employer:  FPGA DESIGN 
 
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Micro Architect Experts @ Hyderabad

Micro Architect Experts @ Hyderabad

Job Details : ASIC/FPGA Design(Digital)  Detailed Description of the Job Profile: This person will be leading a team of senior engineers. He will be involved in recruiting, training these engineers. He will be responsible for visiting customer site, understanding customer requirements as lead...
Updated:  2012-Jul-27 01:28 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: Logic Design Engineer
Experience Level: 3.0 to 15.0 yrsLocation: Bangalore Hyderabad Noida  (India)
Employer:  ASIC FPGA Engineers 

Keywords:  RTL

 
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Logic Design Engineer jobs @ Bangalore

Logic Design Engineer jobs @ Bangalore

Job Details : ASIC/FPGA Design(Digital)  Detailed Description of the Job Profile: This person will be leading a team of senior engineers. He will be involved in recruiting, training these engineers. He will be responsible for visiting customer site, understanding customer requirements as lead...
Updated:  2012-Jul-26 04:13 AM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: Logic Design Engineer
Experience Level: 3.0 to 15.0 yrsLocation: Bangalore Hyderabad Noida  (India)
Employer:  ASIC FPGA Engineers 

Keywords:  RTL

 
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Logic Design Engineer jobs @ Bangalore/Noida/Hyderabad

Logic Design Engineer jobs @ Bangalore/Noida/Hyderabad

Job Details : ASIC/FPGA Design(Digital)  Detailed Description of the Job Profile: This person will be leading a team of senior engineers. He will be involved in recruiting, training these engineers. He will be responsible for visiting customer site, understanding customer requirements as lead...
Updated:  2012-Jul-25 02:51 AM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: Logic Design Engineer
Experience Level: 3.0 to 15.0 yrsLocation: Bangalore Hyderabad Noida  (India)
Employer:  ASIC FPGA Engineers 

Keywords:  RTL

 
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Frontend Design Engineer Job

Frontend Design Engineer Job

RTL Design Engineer
Updated:  2012-Jul-20 04:15 AM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: Frontend Design Engineer
Experience Level: 3.0 to 15.0 yrsLocation: Bangalore  (India)
Employer:  ASIC FPGA Engineers 

Keywords:  RTL

 
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ASIC Design Engineer

ASIC Design Engineer

Job description: Position:  ASIC Design Engineer, Experience: 3 -15 Years, Location: Bangalore/Hyderabad/Pune, Qualification: B. E/B. Tech/M. Tech. Email your CV to  saku@vlsijobs.net  
Updated:  2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: ASIC Design Engineer
Experience Level: 3.0 to 15.0 yrsLocation: Bangalore Pune Hyderabad  (India)
Employer:  ASIC FPGA Engineers 

Keywords:  RTL

 
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Hiring ::ASIC Professionals at Bangalore

Hiring ::ASIC Professionals at Bangalore

Requirement :   Category:Semiconductor Jobs Designation :ASIC (Verification/PD/DFT/STA) Location :Bangalore Qualification :BE/ME/BTECH/MTECH Experience :3-8 yrs   Experience :   Looking for 3+ year of Candidate in ASIC Domain .   Description -Physical Design   Implementation of multimillion gate...
Updated:  2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: IT ProductsRole: ASIC Professionals
Experience Level: 3.0 to 10.0 yrsLocation: Bangalore  (India)
Employer:  ASIC FPGA Engineers 

Keywords:  ASIC

 
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Job:Physical Designer at Bangalore

Job:Physical Designer at Bangalore

Requirement :   Category:Semiconductor Jobs Designation :ASIC Physical Design Engineer Location :Bangalore Qualification :BE/ME/BTECH/MTECH Experience :3-8 yrs
Updated:  2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: Physical Design Engineer
Experience Level: 3.0 to 10.0 yrsLocation: Bangalore  (India)
Employer:  ASIC FPGA Engineers 

Keywords:  Physical Design ASIC

 
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Fpga Emulation, FPGA Emulation, Cambio Consulting, Bangalore

Fpga Emulation, FPGA Emulation, Cambio Consulting, Bangalore

Designation Senior Engineer - FPGA Emulation Location Bangalore Qualification B.E /M.E/ B.Tech/M.Tech Experience 4 to 7 years Domain No of Posts Description ·          Hands-on experience in XILINX FPGA prototyping (preferably on Multi-FPGA SoC designs). ·          Working experience in FPGA...
Updated:  2013-Apr-08 11:44 AM
By: Cambio ConsultingRole: FPGA Emulation
Experience Level: 4.0 to 7.0 yrsLocation: Bangalore  (India)
Employer:  Cambio Consulting 

Keywords:  Fpga Emulation

 
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Bangalore Jobs open for FPGA Emulation

Bangalore Jobs open for FPGA Emulation

Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs,debug and resolve them with greater...
Updated:  2013-Jun-13 11:45 AM
By: Cosmic ConsultantsIndustry: ITRole: FPGA Emulation
Location: Not Specified 

Keywords:  Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs debug and resolve them with greater quality He/she owns the responsibility of the logical block of the SOC for Emulation Pre-Silicon Validation using FPGA System Debug of hw fw FPGA environment during bring-up of FPGA model Skill Sets Experience in emulation of the RTL into FPGA synthesize the RTL for Emulation compatible bring up interfaces like FPGA prototype. Languages: Verilog C system C Platforms: Palladium from Cadence Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs debug and resolve them with greater quality He/she owns the responsibility of the logical block of the SOC for Emulation Pre-Silicon Validation using FPGA System Debug of hw fw FPGA environment during bring-up of FPGA model Skill Sets Experience in emulation of the RTL into FPGA synthesize the RTL for Emulation compatible bring up interfaces like FPGA prototype. Languages: Verilog C system C Platforms: Palladium from Cadence Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs debug and resolve them with greater quality He/she owns the responsibility of the logical block of the SOC for Emulation Pre-Silicon Validation using FPGA System Debug of hw fw FPGA environment during bring-up of FPGA model Skill Sets Experience in emulation of the RTL into FPGA synthesize the RTL for Emulation compatible bring up interfaces like FPGA prototype. Languages: Verilog C system C Platforms: Palladium from Cadence Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs debug and resolve them with greater quality He/she owns the responsibility of the logical block of the SOC for Emulation Pre-Silicon Validation using FPGA System Debug of hw fw FPGA environment during bring-up of FPGA model Skill Sets Experience in emulation of the RTL into FPGA synthesize the RTL for Emulation compatible bring up interfaces like FPGA prototype. Languages: Verilog C system C Platforms: Palladium from Cadence

 
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Bangalore Jobs open for FPGA Emulation

Bangalore Jobs open for FPGA Emulation

Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs,debug and resolve them with greater...
Updated:  2013-May-30 10:47 AM
By: Cosmic ConsultantsIndustry: ITRole: FPGA Emulation
Location: Not Specified 

Keywords:  Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs debug and resolve them with greater quality He/she owns the responsibility of the logical block of the SOC for Emulation Pre-Silicon Validation using FPGA System Debug of hw fw FPGA environment during bring-up of FPGA model Skill Sets Experience in emulation of the RTL into FPGA synthesize the RTL for Emulation compatible bring up interfaces like FPGA prototype. Languages: Verilog C system C Platforms: Palladium from Cadence Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs debug and resolve them with greater quality He/she owns the responsibility of the logical block of the SOC for Emulation Pre-Silicon Validation using FPGA System Debug of hw fw FPGA environment during bring-up of FPGA model Skill Sets Experience in emulation of the RTL into FPGA synthesize the RTL for Emulation compatible bring up interfaces like FPGA prototype. Languages: Verilog C system C Platforms: Palladium from Cadence Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs debug and resolve them with greater quality He/she owns the responsibility of the logical block of the SOC for Emulation Pre-Silicon Validation using FPGA System Debug of hw fw FPGA environment during bring-up of FPGA model Skill Sets Experience in emulation of the RTL into FPGA synthesize the RTL for Emulation compatible bring up interfaces like FPGA prototype. Languages: Verilog C system C Platforms: Palladium from Cadence Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs debug and resolve them with greater quality He/she owns the responsibility of the logical block of the SOC for Emulation Pre-Silicon Validation using FPGA System Debug of hw fw FPGA environment during bring-up of FPGA model Skill Sets Experience in emulation of the RTL into FPGA synthesize the RTL for Emulation compatible bring up interfaces like FPGA prototype. Languages: Verilog C system C Platforms: Palladium from Cadence

 
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Bangalore Jobs open for FPGA Emulation

Bangalore Jobs open for FPGA Emulation

Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs,debug and resolve them with greater...
Updated:  2013-May-20 08:01 AM
By: Cosmic ConsultantsIndustry: ITRole: FPGA Emulation
Location: Not Specified 

Keywords:  Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs debug and resolve them with greater quality He/she owns the responsibility of the logical block of the SOC for Emulation Pre-Silicon Validation using FPGA System Debug of hw fw FPGA environment during bring-up of FPGA model Skill Sets Experience in emulation of the RTL into FPGA synthesize the RTL for Emulation compatible bring up interfaces like FPGA prototype. Languages: Verilog C system C Platforms: Palladium from Cadence Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs debug and resolve them with greater quality He/she owns the responsibility of the logical block of the SOC for Emulation Pre-Silicon Validation using FPGA System Debug of hw fw FPGA environment during bring-up of FPGA model Skill Sets Experience in emulation of the RTL into FPGA synthesize the RTL for Emulation compatible bring up interfaces like FPGA prototype. Languages: Verilog C system C Platforms: Palladium from Cadence Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs debug and resolve them with greater quality He/she owns the responsibility of the logical block of the SOC for Emulation Pre-Silicon Validation using FPGA System Debug of hw fw FPGA environment during bring-up of FPGA model Skill Sets Experience in emulation of the RTL into FPGA synthesize the RTL for Emulation compatible bring up interfaces like FPGA prototype. Languages: Verilog C system C Platforms: Palladium from Cadence Position : FPGA Emulation Engineers/Sr.Engineers Experience: 4+ Years Location: Bangalore Job Description FPGA Emulation Porting ASIC RTL on FPGA FPGA specific logic development He/she should be able to validate logical blocks of the SOC and identify bugs debug and resolve them with greater quality He/she owns the responsibility of the logical block of the SOC for Emulation Pre-Silicon Validation using FPGA System Debug of hw fw FPGA environment during bring-up of FPGA model Skill Sets Experience in emulation of the RTL into FPGA synthesize the RTL for Emulation compatible bring up interfaces like FPGA prototype. Languages: Verilog C system C Platforms: Palladium from Cadence

 
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FPGA Design Engineer jobs in Pune

FPGA Design Engineer jobs in Pune

Primary responsibilities Design and coding using VHDL FPGA simulation and verification Lab-based analysis and debug on Hardware platforms FPGA prototyping which may require partitioning the core on two or more FPGAs
Updated:  2012-Nov-03 05:32 AM
By: Roland and AssociatesIndustry: Hardware, IT Products, SemiconductorRole: Design Engineer- FPGA
Experience Level: 2.0 to 5.0 yrsLocation: Pune  (India)
 
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FPGA Design Tool Jobs in Pune

FPGA Design Tool Jobs in Pune

Primary responsibilities Design and coding using VHDL FPGA simulation and verification Lab-based analysis and debug on Hardware platforms FPGA prototyping which may require partitioning the core on two or more FPGAs
Updated:  2012-Nov-03 05:16 AM
By: Roland and AssociatesIndustry: Hardware, IT Products, SemiconductorRole: FPGA design tools (Synopsys Certify and Synplify, Xilinx ISE)
Experience Level: 2.0 to 5.0 yrsLocation: Pune  (India)
 
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FPGA Design Engineer jobs in Pune

FPGA Design Engineer jobs in Pune

Primary responsibilities Design and coding using VHDL FPGA simulation and verification Lab-based analysis and debug on Hardware platforms FPGA prototyping which may require partitioning the core on two or more FPGAs
Updated:  2012-Nov-03 05:08 AM
By: Roland and AssociatesIndustry: Hardware, IT Products, SemiconductorRole: Design Engineer- FPGA
Experience Level: 2.0 to 5.0 yrsLocation: Pune  (India)
 
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FPGA, Design Engineer Job Opening in Bangalore

FPGA, Design Engineer Job Opening in Bangalore

We have openings for Design Engineers for our esteemed client, a Telecom company in Bangalore. Job criteria: • Proficient on Digital design using FPGAs (Xilinx preferred) • Familiar with FPGA design and verification flow. • VHDL coding experience for both RTL and Test bench. • Familiar with...
Updated:  2012-Aug-07 05:57 AM
By: Resource LinkIndustry: Hardware, Communications and NetworkingRole: Design Engineer
Experience Level: 4.0 to 7.0 yrsLocation: Bangalore  (India)
 
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Job Opening for Digital Design Engineers (ASIC/FPGA), Bangalore

Job Opening for Digital Design Engineers (ASIC/FPGA), Bangalore

Looking for professionals with solid experience in Design Design in any of the following areas with 3 – 7 years of relevant experience: Architecture RTL    :Behavioral Modeling, RTL, Synthesis Back End                           : Synthesis, P R, Timing Closure, EMIR, SI Test                     ...
Updated:  2012-Jul-10 11:23 AM
By: PVS ASSOCIATES Industry: IT ProductsRole: Digital Design Engineers
Experience Level: 3.0 to 7.0 yrsLocation: Bangalore (India)
 
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VHDl, verilog, Actel, ALTERA, XILINX, Hiring Fpga Professionals, A Leading Services Company, Bangalore/ Hyderabad /Vizag

VHDl, verilog, Actel, ALTERA, XILINX, Hiring Fpga Professionals, A Leading Services Company, Bangalore/ Hyderabad /Vizag

We have an openings for ASIC FPGA Engineers with leading level5 company in Bangalore/Hyderabad/Vizag locations.Interested candidate please send your updated resume to  viswanadhareddy@fusionservices.in and also call us +919886284972.   Job Type:Permanent Exp:3 to7Yrs Locations:Bangalore/Hyderaba...
Updated:  2012-Jul-12 08:47 AM
By: Fusion Intellect ServicesIndustry: SemiconductorRole: Hiring Fpga Professionals
Experience Level: 3.0 to 6.0 yrsLocation: Bangalore Hyderabad Vizag  (India)
 
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VHDL Design Engineer Jobs in Pune - shekar@roljobs.com

VHDL Design Engineer Jobs in Pune - shekar@roljobs.com

The Role  Primary responsibilities will include     Design and coding using VHDL     FPGA simulation and verification     Lab-based analysis and debug on Hardware platforms     FPGA prototyping which may require partitioning the core on two or more FPGAs
Updated:  2012-Mar-08 07:32 PM
By: Roland and AssociatesIndustry: Hardware, Communications and Networking, IT Products, Semiconductor, IT ServicesRole: VHDL
Experience Level: 2.0 to 4.0 yrsLocation: Pune  (India)
 
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Jobs Design Staff Engineer at Bangalore

Jobs Design Staff Engineer at Bangalore

* About 5 years experience in SoC Verification and Validation * Should have experience with both Verilog/System Verilog based verification and FPGA validation
Updated:  2013-Apr-19 12:02 PM
By: Cambio ConsultingIndustry: SemiconductorRole: Jobs Design Staff Engineer at Bangalore
Experience Level: 5.0 to 10.0 yrsLocation: Bangalore  (India)

Keywords:  FPGA VLSI SOC verilog

 
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