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Logic Equivalent Checking Jobs

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ASIC, Library Development (Timing and Physical), Synthesis, Auto Placement and Routing, DFT Scan implementation, Clock Tree implementation, Static Timing Analysis, Logic Equivalence Checking, DRC, LVS, DFM, parasitic extraction flows., Physical Design Engineer, A Leading IT Company

In-depth understanding of the ASIC design flow including all aspects of implementation of complex digital cores. Specific areas of expertise are: Library Development (Timing and Physical), Synthesis, Auto Placement and Routing, DFT Scan implementation, Clock Tree implementation, Static Timing...

Updated: 2012-Apr-16 06:20 AM

By: AIM PLUS STAFFING SOLUTIONSIndustry: IT ProductsRole: Physical Design Engineer

Experience Level: 4.0 to 10.0 yrsLocation: (India)

Employer: A Leading IT Company

Keywords: ASIC Library Development (Timing and Physical) Synthesis Auto Placement and Routing DFT Scan implementation Clock Tree implementation Static Timing Analysis Logic Equivalence Checking DRC LVS DFM parasitic extraction flows.

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Document Checking

Updated: 2012-Mar-30 05:13 AM

By: Good Relations ConsultantsIndustry: Investment BankingRole: Document Checking

Experience Level: 3.0 to 6.0 yrsLocation: Bangalore/Jaipur/Mumbai

Keywords: Document Checking

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Document Checking

Updated: 2012-Mar-20 05:35 AM

By: Good Relations ConsultantsRole: Document Checking

Experience Level: 3.0 to 6.0 yrsLocation: Investment Banking Bangalore/Jaipur/Mumbai

Keywords: Document Checking

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DFT Engineer jobs in Bangalore

Position: DFT Engineer/Lead Qualification: B.Tech/B.E (ECE/EE)/M.S/M.Tech (VLSI/Digital Electronics) Experience: 4-7 yrs Location: Hyderabad Job Description: Ideal Candidate will be part of the DFT team, providing DFT services to a wide range of silicon companies. He/She will work on all aspects...

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

View Job

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

View Job

Refer

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DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

View Job

Refer

Apply

DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

View Job

Refer

Apply

DFT Engineer jobs in Bangalore

Updated: 2012-May-05 07:37 AM

By: Roland and AssociatesIndustry: HardwareRole: DFT Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: (Design for Test) DFT Logic bist "Memory BIST" "Boundary scan" "Full Scan" "Scan compression" ATPG "Logic design" "Logic Synthesis" "Logic Equivalent Checking" "Static Timing Analysis" "Signal Integrity checks" "Backend timing closure"

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