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Memory BIST Jobs

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BIST Simulation Expert

BIST Simulation Expert

DFT Engineer
Updated:  2012-Jul-30 12:57 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: Semiconductor
Experience Level: 9.0 to 10.0 yrsLocation: Bangalore (India)
Employer:  DFT Engineers 

Keywords:  “ATPG” “DFT”

 
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BIST Simulation Expert

BIST Simulation Expert

DFT Engineer
Updated:  2012-Jul-30 12:57 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: Semiconductor
Experience Level: 8.0 to 9.0 yrsLocation: Bangalore (India)
Employer:  DFT Engineers 

Keywords:  “ATPG” “DFT”

 
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BIST Simulation Expert

BIST Simulation Expert

DFT Engineer
Updated:  2012-Jul-30 12:57 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: Semiconductor
Experience Level: 7.0 to 8.0 yrsLocation: Bangalore (India)
Employer:  DFT Engineers 

Keywords:  “ATPG” “DFT”

 
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BIST Simulation Expert

BIST Simulation Expert

DFT Engineer
Updated:  2012-Jul-30 12:57 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: Semiconductor
Experience Level: 6.0 to 7.0 yrsLocation: Bangalore (India)
Employer:  DFT Engineers 

Keywords:  “ATPG” “DFT”

 
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BIST Simulation Expert

BIST Simulation Expert

DFT Engineer
Updated:  2012-Jul-30 12:57 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: Semiconductor
Experience Level: 5.0 to 6.0 yrsLocation: Bangalore (India)
Employer:  DFT Engineers 

Keywords:  “ATPG” “DFT”

 
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BIST Simulation Expert

BIST Simulation Expert

DFT Engineer
Updated:  2012-Jul-30 12:57 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: Semiconductor
Experience Level: 4.0 to 5.0 yrsLocation: Bangalore (India)
Employer:  DFT Engineers 

Keywords:  “ATPG” “DFT”

 
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BIST Simulation Expert

BIST Simulation Expert

DFT Engineer
Updated:  2012-Jul-30 12:57 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: Semiconductor
Experience Level: 3.0 to 4.0 yrsLocation: Bangalore (India)
Employer:  DFT Engineers 

Keywords:  “ATPG” “DFT”

 
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Jobs for Memory Design

Jobs for Memory Design

#Electronics Engg, #Exposure to CMOS fundamentals, #Exposure to VLSI design, #Knowledge of design principles and practices, #Good College #Experience with circuit design, IC layout, UNIX scripts, and CAD verification, #Understanding of key SRAM blocks viz. Sense Amplifiers, Row Decoders, IOs...
Updated:  2012-Aug-11 12:00 AM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: Memory Design
Experience Level: 2.0 to 4.0 yrsLocation: Noida (India)
Employer:  Memory Design 
 
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Jobs for Non Volatile Memory Design @ Greater Noida

Jobs for Non Volatile Memory Design @ Greater Noida

Design of Non-Volatile memory IPs – Flash standard CMOS based solutions. emerging technologies like PCM Involves – design/analysis of competitive blocks like Op-Amps , Regulators, Current Voltage References, Sense-Amplifier, Mixed Signal design Memory Blocks, Charge-pump, Circuit Oscillators for...
Updated:  2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: Non volatile Memory
Experience Level: 1.0 to 5.0 yrsLocation: Graeter Noida (India)
Employer:  Memory Design 
 
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Memory Layout Jobs in Delhi/NCR

Memory Layout Jobs in Delhi/NCR

Responsibilities : - Design of back end Memory Layout with compiler development. - Work on Layout Tiling, Netlist Tiling.
Updated:  2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Role: Embedded Engineer
Experience Level: 2.0 to 5.0 yrsLocation: New Delhi NCR  (India)
Employer:  Memory Layout 
 
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Jobs for Memory Design @ Greater Noida

Jobs for Memory Design @ Greater Noida

Exposure to CMOS fundamentals Exposure to VLSI design Experience with circuit design, IC layout, UNIX scripts, and CAD verification Proficient in DRC/LVS/parasitic extraction/Spice simulations, 
Updated:  2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: Memory Design
Experience Level: 2.0 to 6.0 yrsLocation: Greater Noida (India)
Employer:  Memory Design 
 
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timing, clocking, BIST, Front End Digital Engineer, Leading Product Development Company, Bangalore

timing, clocking, BIST, Front End Digital Engineer, Leading Product Development Company, Bangalore

1. Drive key aspects of IP specification (timing, area, power, clocking, BIST/DFT, Application requirements etc.) 2. Developing micro-architecture of Comm. Peripherals, Memory/Flash Controllers given high level IP requirements. 3. RTL development for IPs meeting the Area/Timing and power goals...
Updated:  2012-Jun-27 07:21 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: Front End Digital Engineer
Experience Level: 6.0 to 12.0 yrsLocation: Bangalore  (India)
Employer:  Leading Product Development Company 
 
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DFT Engineer jobs at Bangalore

DFT Engineer jobs at Bangalore

40nm/28nm design for test (DFT) methodology development and implementation      You will participate in block and chip level DFT architecture design, working towards the successful implementation of LogicVision LogicBIST, TestKompress ATPG, and RAM BIST in our chips.      Role Responsibility:-...
Updated:  2013-Mar-12 12:47 PM
By: Roland and AssociatesIndustry: SemiconductorRole: DFT
Experience Level: 3.0 to 12.0 yrsLocation: Bangalore  (India)
 
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DFT Experts @ Bangalore

DFT Experts @ Bangalore

Role:DFT Engineer Responsibilities: 40nm/28nm design for test (DFT) methodology development and implementation      You will participate in block and chip level DFT architecture design, working towards the successful implementation of LogicVision LogicBIST, TestKompress ATPG, and RAM BIST in our...
Updated:  2013-Feb-04 09:33 AM
By: Roland and AssociatesIndustry: SemiconductorRole: DFT
Experience Level: 2.0 to 13.0 yrsLocation: Bangalore  (India)
 
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DFT, ASIC, ATPG, BIST, VLSI, DFT Engineer, Leading IT Professional Service Provider, Bangalore

DFT, ASIC, ATPG, BIST, VLSI, DFT Engineer, Leading IT Professional Service Provider, Bangalore

Must have prior full-chip DFT leadership experience handling large complex ASIC/SoC and should have handled at least one SoC tapeout.   Should have hands-on experience with scan synthesis, scan DRC fixing, MBIST, LBIST, JTAG (IEEE 1149.1), On-chip scan compression techniques   Block level and...
Updated:  2013-Mar-16 09:31 AM
By: Cambio ConsultingIndustry: HardwareRole: DFT Engineer
Experience Level: 3.0 to 13.0 yrsLocation: Bangalore  (India)
 
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BIST controllers, Flash Controller, Digital wrappers, IP DV Engineer, MNC Client of Peopleplusindia in Semiconductor Domain, Bangalore

BIST controllers, Flash Controller, Digital wrappers, IP DV Engineer, MNC Client of Peopleplusindia in Semiconductor Domain, Bangalore

Job Posting Title                                IP DV Engineer Job Description          This role involves:   Verification of system and peripheral IP modules commonly used for various functions in automotive systems to ensure 0 bug IPs. Some IP examples include Real-time BIST controllers,...
Updated:  2012-Jun-27 07:30 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: IP DV Engineer
Experience Level: 4.0 to 8.0 yrsLocation: Bangalore  (India)
Employer:  MNC Client of Peopleplusindia in Semiconductor Domain 
 
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Jobs for Linux Drivers, Boot Loader in Bangalore

Jobs for Linux Drivers, Boot Loader in Bangalore

Job description:   1. Bachelor’s degree in EE/CS and 4-9 years of experience in the area of platform software development. 2. Strong "C" and embedded programming and extremely strong debugging skills (using gdb, kdbg etc.) and JTAG tools 3. Knowledge of HW platforms, processors, memory,...
Updated:  2013-May-13 05:54 AM
By: Cambio ConsultingIndustry: IT ProductsRole: Software Engineer
Experience Level: 4.0 to 9.0 yrsLocation: Bangalore (India)
 
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BIOS debug expert jobs in Bangalore

BIOS debug expert jobs in Bangalore

Job Description: In this position, you will be responsible for working with BIOS development and architect to isolate and debug FW sightings and contribute to design and development of validation collaterals.  Your responsibilities will include but not be limited to: -  Develop knowledge on BIOS...
Updated:  2012-May-15 11:00 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: BIOS debug Expert
Experience Level: 5.0 to 12.0 yrsLocation: Not Specified (India)
Employer:  BIG 4 Consulting Firm 
 
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Debug Pre-boot, ACPI, SMBIOS, PCIE, BIOS debug Expert, BIG 4 Consulting Firm

Debug Pre-boot, ACPI, SMBIOS, PCIE, BIOS debug Expert, BIG 4 Consulting Firm

Job Description: In this position, you will be responsible for working with BIOS development and architect to isolate and debug FW sightings and contribute to design and development of validation collaterals.  Your responsibilities will include but not be limited to: -  Develop knowledge on BIOS...
Updated:  2012-May-15 10:59 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: BIOS debug Expert
Experience Level: 5.0 to 12.0 yrsLocation: Not Specified (India)
Employer:  BIG 4 Consulting Firm 
 
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 Front End Digital jobs in Bangalore

Front End Digital jobs in Bangalore

1. Drive key aspects of IP specification (timing, area, power, clocking, BIST/DFT, Application requirements etc.) 2. Developing micro-architecture of Comm. Peripherals, Memory/Flash Controllers given high level IP requirements. 3. RTL development for IPs meeting the Area/Timing and power goals...
Updated:  2012-Jun-27 07:38 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: Front End Digital Engineer
Experience Level: 6.0 to 12.0 yrsLocation: Bangalore  (India)
Employer:  Leading Product Development Company