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timing, clocking, BIST, Front End Digital Engineer, Leading Product Development Company, Bangalore
1. Drive key aspects of IP specification (timing, area, power, clocking, BIST/DFT, Application requirements etc.) 2. Developing micro-architecture of Comm. Peripherals, Memory/Flash Controllers given high level IP requirements. 3. RTL development for IPs meeting the Area/Timing and power goals...
Updated:
2012-May-02 08:51 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: Front End Digital Engineer
Experience Level: 6.0 to 12.0 yrsLocation: Bangalore (India)
Employer:
Leading Product Development Company
Power Estimation, Clock Gating, Power Gating, Power Estimation and Modeling Lead, World leader in Visual Computing Technologies
Architect and develop Power Estimation Models for key use-cases, Leakage, and IO Power. Design the tools based on these models, and develop solid validation methodology/infrastructures. Lead a team, interface/coordinate with external teams in the US and India that provides necessary input data...
Updated:
2012-May-18 07:34 PM
By: Spectrum ConsultantsIndustry: HardwareRole: Power Estimation and Modeling Lead
Experience Level: 3.0 to 8.0 yrsLocation: (India)
ASIC, Library Development (Timing and Physical), Synthesis, Auto Placement and Routing, DFT Scan implementation, Clock Tree implementation, Static Timing Analysis, Logic Equivalence Checking, DRC, LVS, DFM, parasitic extraction flows., Physical Design Engineer, A Leading IT Company
In-depth understanding of the ASIC design flow including all aspects of implementation of complex digital cores. Specific areas of expertise are: Library Development (Timing and Physical), Synthesis, Auto Placement and Routing, DFT Scan implementation, Clock Tree implementation, Static Timing...
Updated:
2012-Apr-16 06:20 AM
By: AIM PLUS STAFFING SOLUTIONSIndustry: IT ProductsRole: Physical Design Engineer
Experience Level: 4.0 to 10.0 yrsLocation: (India)
Employer:
A Leading IT Company
Front End Digital jobs in Bangalore
1. Drive key aspects of IP specification (timing, area, power, clocking, BIST/DFT, Application requirements etc.) 2. Developing micro-architecture of Comm. Peripherals, Memory/Flash Controllers given high level IP requirements. 3. RTL development for IPs meeting the Area/Timing and power goals...
Updated:
2012-May-02 08:56 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: Front End Digital Engineer
Experience Level: 6.0 to 12.0 yrsLocation: Bangalore (India)
Employer:
Leading Product Development Company
Front End Digital jobs in Bangalore
1. Drive key aspects of IP specification (timing, area, power, clocking, BIST/DFT, Application requirements etc.) 2. Developing micro-architecture of Comm. Peripherals, Memory/Flash Controllers given high level IP requirements. 3. RTL development for IPs meeting the Area/Timing and power goals...
Updated:
2012-May-02 08:55 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: Front End Digital Engineer
Experience Level: 6.0 to 12.0 yrsLocation: Bangalore (India)
Employer:
Leading Product Development Company
Semicon Jobs (Physical Design)
JD: . Qualification: BE/ME/BTECH/MTECH . Implementation of multimillion gates SoC designs in cutting edge process technologies (28nm, 45nm 65nm) . Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing...
Updated:
2012-Mar-14 02:33 PM
By: Roland and AssociatesRole: Physical Design Engineer/Lead
Experience Level: 3.0 to 15.0 yrsLocation: (India)
45nm, physical verification, STA, Physical Design Engineer, Whizchip Design Technologies Private limited
Physical Design Engineer At least 3 years of experience in physical design, with at least one project in 45nm or below Experience in standard industry tools covering aspects of place route and timing closure Should be able to independently handle execution from netlist to GDSII Should be...
Updated:
2012-May-22 04:30 AM
By: WHIZCHIPIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 4.0 to 8.0 yrsLocation: (India)
Employer:
Whizchip Design Technologies Private limited
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