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Mixed Signal Verification(AMS) Engineer Jobs in Bangalore & Hyderabad
BASIC: -Experience in the field of Mixed Signal/Analog Verification, and VHDL real number modeling. -Proficient in VHDL, Spice and knowledge about Verilog. -Experience on simulations with Modelsim, Nanosim, NCSim,Spice,Spectre,Cadence. - Experience in Automation languages like Perl,Shell,TCL...
Updated:
2012-Jul-24 10:46 AM
By: Fusion Intellect ServicesIndustry: SemiconductorRole: Mixed signal verification Engineer
Experience Level: 2.0 to 13.0 yrsLocation: Bangalore,Noida (India)
Mixed Signal Verification(AMS) Engineer Jobs in Bangalore & Hyderabad
BASIC: -Experience in the field of Mixed Signal/Analog Verification, and VHDL real number modeling. -Proficient in VHDL, Spice and knowledge about Verilog. -Experience on simulations with Modelsim, Nanosim, NCSim,Spice,Spectre,Cadence. - Experience in Automation languages like Perl,Shell,TCL...
Updated:
2012-Jul-20 10:06 AM
By: Fusion Intellect ServicesIndustry: SemiconductorRole: Mixed signal verification Engineer
Experience Level: 2.0 to 13.0 yrsLocation: Bangalore,Noida (India)
Mixed Signal Verification(AMS) Engineer Jobs in Bangalore & Hyderabad
BASIC: -Experience in the field of Mixed Signal/Analog Verification, and VHDL real number modeling. -Proficient in VHDL, Spice and knowledge about Verilog. -Experience on simulations with Modelsim, Nanosim, NCSim,Spice,Spectre,Cadence. - Experience in Automation languages like Perl,Shell,TCL...
Updated:
2012-Jul-13 04:14 AM
By: Fusion Intellect ServicesIndustry: SemiconductorRole: Mixed signal verification Engineer
Experience Level: 2.0 to 13.0 yrsLocation: Bangalore,Noida (India)
Mixed Signal Verification(AMS) Engineer Jobs in Bangalore & Hyderabad
BASIC: -Experience in the field of Mixed Signal/Analog Verification, and VHDL real number modeling. -Proficient in VHDL, Spice and knowledge about Verilog. -Experience on simulations with Modelsim, Nanosim, NCSim,Spice,Spectre,Cadence. - Experience in Automation languages like Perl,Shell,TCL...
Updated:
2012-Jul-16 10:40 AM
By: Fusion Intellect ServicesIndustry: SemiconductorRole: Mixed signal verification Engineer
Experience Level: 2.0 to 13.0 yrsLocation: Bangalore,Noida (India)
VHDL, Spice, Modelsim, Nanosim, Mixed signal verification Engineer, A Leading Services Company, Bangalore Hyderabad
BASIC: -Experience in the field of Mixed Signal/Analog Verification, and VHDL real number modeling. -Proficient in VHDL, Spice and knowledge about Verilog. -Experience on simulations with Modelsim, Nanosim, NCSim,Spice,Spectre,Cadence. - Experience in Automation languages like Perl,Shell,TCL...
Updated:
2012-Jun-25 07:11 AM
By: Fusion Intellect ServicesIndustry: SemiconductorRole: Mixed signal verification Engineer
Experience Level: 2.0 to 13.0 yrsLocation: Bangalore Hyderabad (India)
VHDL, Spice, Modelsim, Nanosim, Mixed signal verification Engineer, A Leading Services Company, Bangalore,Noida
BASIC: -Experience in the field of Mixed Signal/Analog Verification, and VHDL real number modeling. -Proficient in VHDL, Spice and knowledge about Verilog. -Experience on simulations with Modelsim, Nanosim, NCSim,Spice,Spectre,Cadence. - Experience in Automation languages like Perl,Shell,TCL...
Updated:
2012-May-14 11:51 AM
By: Fusion Intellect ServicesIndustry: SemiconductorRole: Mixed signal verification Engineer
Experience Level: 1.5 to 13.0 yrsLocation: Bangalore,Noida (India)
Verification Engineer Jobs
Would be required to take responsibility of Verification Plan, Environment development, Functional Coverage achievement, Evolution of Robust Coverage for a range of Digital and Mixed Signal IPs.
Updated:
2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: Verification Engineer
Experience Level: 2.0 to 5.0 yrsLocation: Noida (India)
Employer:
Design Verification
Verification Engineer Jobs
Would be required to take responsibility of Verification Plan, Environment development, Functional Coverage achievement, Evolution of Robust Coverage for a range of Digital and Mixed Signal IPs. Would require the ability to perform well in a team-based work structure.
Updated:
2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: Verification Engineer
Experience Level: 2.0 to 5.0 yrsLocation: Greater Noida (India)
Employer:
Design Verification
specman, Specman, No Company Assigned, Bangalore
Verification Engineer Exp : 2 to 7 years Skills : Specman-E, Verilog, VHDL, e, VCS/NCSim/ModelSim Preferable Skills : ARM based SOC verification using C/C++, Perl/TCL scripting Responsibilities : The individual will be responsible for top level verification of mobile platform SOCs. Would be...
Updated:
2012-Jul-23 10:17 AM
By: SIE Brains TechnologyRole: Specman
Experience Level: 2.0 to 7.0 yrsLocation: Bangalore (India)
Jobs for Verification Engineer @ Greater Noida
SystemVerilog, ‘e’, VHDL/Verilog language knowledge, UNIX, Perl, Tcl, etc. - Verification environment development/hands-on in Verilog/VHDL based environment - Work experience on simulation tools like SPECMAN, VManager, NCSIM, MODELSIM etc
Updated:
2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: Verification Engineer
Experience Level: 2.0 to 5.0 yrsLocation: Grater Noida (India)
Employer:
Design Verification
ASIC Design Verification Lead @ Pune - Salary 30 Lakhs+
The Senior Design Engineer would be responsible for design verification and implementation of test-benches for key EEBU technologies such as Wireless LAN, Bluetooth, GPS, etc. The role is a Technical Lead role who can independently handle end to end verification. ...
Updated:
2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: ASIC Design Verification
Experience Level: 10.0 to 15.0 yrsLocation: Pune (India)
Employer:
Design Verification
ASIC Design Verification Lead @ Bangalore - Salary 30 Lakhs+
The Senior Design Engineer would be responsible for design verification and implementation of test-benches for key EEBU technologies such as Wireless LAN, Bluetooth, GPS, etc. The role is a Technical Lead role who can independently handle end to end verification. ...
Updated:
2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: ASIC Design Verification
Experience Level: 10.0 to 15.0 yrsLocation: Bangalore (India)
Employer:
Design Verification
Sr.ASIC Verification Engineer(Ethernet/USB/PCI) jobs @ Pune
Sr.ASIC Verification Engineer(Ethernet/USB/PCI) jobs @ Pune with a leading Product based MNC Position :Senior ASIC Verification Engineer Experience :4-12 years Location :Pune Qualification : Bachelors/Masters in Electronics and Communication or Computer Science Engineering. Email...
Updated:
2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: SENIOR ASIC Verification Engineer
Experience Level: 4.0 to 12.0 yrsLocation: Pune (India)
Employer:
Design Verification
Jobs : ASIC Design Verification Lead Engineer @ Pune
Role Responsibility:- The Senior Design Engineer would be responsible for design verification and implementation of test-benches for key EEBU technologies such as Wireless LAN, Bluetooth, GPS, etc. The role is a Technical Lead role who can independently handle end to end verification. ...
Updated:
2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: ASIC Design Verification Lead
Experience Level: 9.0 to 15.0 yrsLocation: Pune (India)
Employer:
Design Verification
Jobs : ASIC Design Verification Lead Engineer @ Bangalore
Role Responsibility:- The Senior Design Engineer would be responsible for design verification and implementation of test-benches for key EEBU technologies such as Wireless LAN, Bluetooth, GPS, etc. The role is a Technical Lead role who can independently handle end to end verification. ...
Updated:
2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: ASIC Design Verification Lead
Experience Level: 9.0 to 15.0 yrsLocation: Bangalore (India)
Employer:
Design Verification
ASIC Design Verification Lead
Exp : 10+ Yrs Experienced in definition and implementation of complex test benches with System Verilog/ Vera/ SystemC/ Specman for verification of complex blocks for Bluetooth, WLAN and GPS Experienced in Verilog, VCS/NCsim, Modeltech. Proven track record of taping out chips to production...
Updated:
2012-May-07 10:40 AM
By: SIE Brains TechnologyIndustry: IT ProductsRole: Design Verification Lead
Experience Level: 10.0 to 15.0 yrsLocation: Pune
ASIC Design Verification Lead
Exp : 10+ Yrs Experienced in definition and implementation of complex test benches with System Verilog/ Vera/ SystemC/ Specman for verification of complex blocks for Bluetooth, WLAN and GPS Experienced in Verilog, VCS/NCsim, Modeltech. Proven track record of taping out chips to production...
Updated:
2012-May-07 10:40 AM
By: SIE Brains TechnologyIndustry: IT ProductsRole: Design Verification Lead
Experience Level: 10.0 to 15.0 yrsLocation: Pune
ASIC Design Verification Lead
Exp : 10+ Yrs Experienced in definition and implementation of complex test benches with System Verilog/ Vera/ SystemC/ Specman for verification of complex blocks for Bluetooth, WLAN and GPS Experienced in Verilog, VCS/NCsim, Modeltech. Proven track record of taping out chips to production...
Updated:
2012-May-07 10:40 AM
By: SIE Brains TechnologyIndustry: IT ProductsRole: Design Verification Lead
Experience Level: 10.0 to 15.0 yrsLocation: Pune
ASIC Design Verification Lead
Exp : 10+ Yrs Experienced in definition and implementation of complex test benches with System Verilog/ Vera/ SystemC/ Specman for verification of complex blocks for Bluetooth, WLAN and GPS Experienced in Verilog, VCS/NCsim, Modeltech. Proven track record of taping out chips to production...
Updated:
2012-May-07 10:40 AM
By: SIE Brains TechnologyIndustry: IT ProductsRole: Design Verification Lead
Experience Level: 10.0 to 15.0 yrsLocation: Pune
ASIC Design Verification Lead
Exp : 10+ Yrs Experienced in definition and implementation of complex test benches with System Verilog/ Vera/ SystemC/ Specman for verification of complex blocks for Bluetooth, WLAN and GPS Experienced in Verilog, VCS/NCsim, Modeltech. Proven track record of taping out chips to production...
Updated:
2012-May-07 10:40 AM
By: SIE Brains TechnologyIndustry: IT ProductsRole: Design Verification Lead
Experience Level: 10.0 to 15.0 yrsLocation: Pune
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