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Physical Design Jobs - Hiring
Ability to close designs at advanced nodes like 65nm or below required. The person will be accountable for floor planning, place route, clock tree design, timing closure, noise analysis, power analysis, signoff (SSTA/Crosstalk) and low power digital flows for various application areas in the...
Updated:
2013-Mar-20 11:47 AM
By: Cambio ConsultingIndustry: SemiconductorRole: SSE
Experience Level: 3.5 to 15.0 yrsLocation: Bangalore (India)
Physical Design Engineer Jobs @ Bangalore/Malaysis
Physical Design Engineer Jobs @ Bangalore/Malaysis Client of Roland Associates Skills : Physical design,SOC encounter,Backend design,Netlist to GDS Experience : 3-8 years Location : Bangalore,Malaysia SoC and Block Level Floor planning Experience in SOC encounter. Netlist to GDS exposure with...
Updated:
2013-May-18 07:19 AM
By: Roland and AssociatesIndustry: SemiconductorRole: Physical design Engineer
Experience Level: 3.0 to 8.0 yrsLocation: Bangalore (India)
Openings In Bangalore for Physical design engieer
experience in logic implementation / physical design / Electrical Analysis / Macro design Hands on working exposure to Synthesis and/or Custom design in 500Mhz-2Ghz frequency Exposure to Design Compiler, IC Compiler , Z Route, Timing using PT/PTSI, Physical verification ...
Updated:
2013-Apr-06 11:03 AM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 5.0 to 10.0 yrsLocation: Bangalore (India)
Jobs on Asic Physical Design @ Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-May-20 12:08 PM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 4.0 to 15.0 yrsLocation: Bangalore (India)
Asic Physical Design jobs@ Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-May-18 10:49 AM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 4.0 to 15.0 yrsLocation: Bangalore (India)
Jobs on Asic Physical Design @ Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-May-18 10:45 AM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 4.0 to 15.0 yrsLocation: Bangalore (India)
Physical Design Openings @ Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-May-18 10:43 AM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 4.0 to 15.0 yrsLocation: Bangalore (India)
Physical Design Jobs @ Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-May-18 10:42 AM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 4.0 to 15.0 yrsLocation: Bangalore (India)
Hirings for Physical Design Professionals @ Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-May-18 10:40 AM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 4.0 to 15.0 yrsLocation: Bangalore (India)
Jobs In Bangalore for physical design
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-Apr-08 12:58 PM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 2.0 to 15.0 yrsLocation: Bangalore (India)
Jobs on Physical design In Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-Apr-06 11:08 AM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 2.0 to 15.0 yrsLocation: Bangalore (India)
Jobs In Bangalore for physical design
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-Apr-06 11:06 AM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 2.0 to 15.0 yrsLocation: Bangalore (India)
Physical Design Hirings In Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-Apr-06 11:04 AM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 2.0 to 15.0 yrsLocation: Bangalore (India)
Asic Physical Design Jobs in Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-Mar-21 01:04 PM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 8.0 to 13.0 yrsLocation: Bangalore (India)
Asic Physical Design Jobs in Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-Mar-19 12:21 PM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 8.0 to 13.0 yrsLocation: Bangalore (India)
Asic Physical Design Jobs in Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-Mar-18 12:34 PM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 8.0 to 13.0 yrsLocation: Bangalore (India)
Hirings for Physical Design Engineers in Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-Mar-08 12:39 PM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 8.0 to 13.0 yrsLocation: Bangalore (India)
Jobs in Bangalore for Physical Design Engineers
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-Mar-06 12:23 PM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 8.0 to 13.0 yrsLocation: Bangalore (India)
Jobs in Bangalore for Physical Design Engineers
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-Mar-04 12:49 PM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 8.0 to 13.0 yrsLocation: Bangalore (India)
Hirings for Physical Design Engineers in Bangalore
Floorplan, Place Route, Placement, Netlist to GDS Implementation, Multimillion gate Soc Designs, Flipchip designs, TCL/Perl/Shell, Tapeouts, Synthesis,Clock Distribution,Extraction,Timing Closure,Signoff,Integration,Partitioning
Updated:
2013-Mar-02 10:44 AM
By: Cambio ConsultingIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 8.0 to 13.0 yrsLocation: Bangalore (India)
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