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EDA, CAD, RTL, GDSII, Tapeout, Design Automation Manager, Client of Aimplusstaffing
Job Description: Provide technical and personnel leadership to a team of engineers involved in developing and deploying state of the art mixed-signal design flows, EDA tool support and methodology development. Work with highly motivated team that focuses on high quality, timely delivery of...
Updated:
2013-Mar-31 07:33 PM
By: AIM PLUS STAFFING SOLUTIONSIndustry: HardwareRole: Design Automation Manager
Experience Level: 10.0 to 15.0 yrsLocation: Not Specified (India)
Physical Design openings in Malaysia
Here is an exiting opportunity in Malaysia for Specialist in Physical Design, CMOS. Know Anyone for this? Reach me on salma@peopleplusindia.com Description In this position, you will be responsible for the implementation of next generation System-on-Chip (SoC) Very Large Scale Integration...
Updated:
2012-Jul-06 06:22 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: Sr Structural Physical Design Engineer
Experience Level: 10.0 to 18.0 yrsLocation: Penang (Malaysia)
Employer:
MNC Client of Peopleplusindia in Semiconductor Domain
Jobs in Malaysia for Physical Design Professionals
Here is an exiting opportunity in Malaysia for Specialist in Physical Design. Description In this position, you will be responsible for the implementation of next generation System-on-Chip (SoC) Very Large Scale Integration (VLSI) designs. Strong communication skills are important as the job...
Updated:
2012-Jul-10 06:59 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: Sr Structural Physical DE
Experience Level: 10.0 to 16.0 yrsLocation: Penang (Malaysia)
Employer:
MNC Client of Peopleplusindia in Semiconductor Domain
Jobs in Malaysia for Physical Design Professionals
Here is an exiting opportunity in Malaysia for Specialist in Physical Design. Description In this position, you will be responsible for the implementation of next generation System-on-Chip (SoC) Very Large Scale Integration (VLSI) designs. Strong communication skills are important as the job...
Updated:
2012-Jul-10 05:05 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: Sr Structural Physical DE
Experience Level: 10.0 to 16.0 yrsLocation: Penang (Malaysia)
Employer:
MNC Client of Peopleplusindia in Semiconductor Domain
Jobs in Malaysia for Physical Design Professionals
Here is an exiting opportunity in Malaysia for Specialist in Physical Design. Description In this position, you will be responsible for the implementation of next generation System-on-Chip (SoC) Very Large Scale Integration (VLSI) designs. Strong communication skills are important as the job...
Updated:
2012-Jul-09 12:56 PM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: Sr Structural Physical DE
Experience Level: 10.0 to 16.0 yrsLocation: Penang (Malaysia)
Employer:
MNC Client of Peopleplusindia in Semiconductor Domain
Jobs in Malaysia for Physical Design Professionals
Here is an exiting opportunity in Malaysia for Specialist in Physical Design. Description In this position, you will be responsible for the implementation of next generation System-on-Chip (SoC) Very Large Scale Integration (VLSI) designs. Strong communication skills are important as the job...
Updated:
2012-Jul-09 04:10 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: Sr Structural Physical DE
Experience Level: 10.0 to 16.0 yrsLocation: Penang (Malaysia)
Employer:
MNC Client of Peopleplusindia in Semiconductor Domain
Jobs in Malaysia for Physical Design Professionals
Here is an exiting opportunity in Malaysia for Specialist in Physical Design. Description In this position, you will be responsible for the implementation of next generation System-on-Chip (SoC) Very Large Scale Integration (VLSI) designs. Strong communication skills are important as the job...
Updated:
2012-Jul-05 11:09 AM
By: PEOPLEPLUS INDIAIndustry: SemiconductorRole: Sr Structural Physical DE
Experience Level: 10.0 to 16.0 yrsLocation: Penang (Malaysia)
Employer:
MNC Client of Peopleplusindia in Semiconductor Domain
Physical design Manager
Physical design Manager Lead and manage a high performance physical design team with complete responsibility on the RTL to tapeout of DSP/SOC chips. The role requires strong technical ability to independently own and execute the physical design of complex high performance DSP-SOC chips in...
Updated:
2013-Apr-30 05:09 AM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: Physical Design Manager
Experience Level: 6.0 to 12.0 yrsLocation: Bangalore (India)
Employer:
Physical Design
Onsite opportunity for Physical design engineer
Physical design engineers Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm, 45nm 65nm) · Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power...
Updated:
2013-May-08 05:46 AM
By: Roland and AssociatesIndustry: SemiconductorRole: Physical design engineer
Experience Level: 3.0 to 8.0 yrsLocation: Malaysia (Malaysia)
ASIC verification jobs in Pune- Leading product MNC, Design Verification, Pune
The candidate will join the wireless verification team and be responsible for the thorough verification of our next generation wireless chips. He/she will be responsible for developing verification plans, building and setting up verification environments, modeling and co-simulation, testvector...
Updated:
2012-Jul-17 07:33 PM
By: Exclusive Portal for VLSI Jobs - An Initiative of Roland & Associates Industry: SemiconductorRole: ASIC verification jobs in Pune- Leading product MNC
Experience Level: 6.0 to 12.0 yrsLocation: Pune (India)
Employer:
Design Verification
VLSI RTL Design Engineer Jobs at Bangalore
Experience: 5 to 11 years Education: BE/B.Tech/M.E/M.Tech Location: Bangalore Knowledge and Skills: VLSI,RTL coding,Verilog,DSL,Chip Expert in RTL Coding with verilog Should have experience in chip tapeout Experience in Micro-architecture, RTL design, Synthesis, Timing closure, Silicon...
Updated:
2013-Mar-19 12:39 PM
By: Roland and AssociatesIndustry: IT ProductsRole: VLSI Design Engineer
Experience Level: 4.0 to 12.0 yrsLocation: Bangalore (India)
Employer:
*IS
Openings for DFT
B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 3+ years of strong, hands on DFT experience Must at least one SoC tapeout experience end-to-end. Should have hands-on experience with scan synthesis, scan DRC fixing, MBIST, LBIST, JTAG (IEEE 1149.1), On-chip scan compression...
Updated:
2012-Aug-18 09:28 AM
By: CambioRole: DFT Engineer
Experience Level: 3.0 to 10.0 yrsLocation: Bangalore (India)
Employer:
Cambio Consulting India Pvt Ltd
Openings for DFT
B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 3+ years of strong, hands on DFT experience Must at least one SoC tapeout experience end-to-end. Should have hands-on experience with scan synthesis, scan DRC fixing, MBIST, LBIST, JTAG (IEEE 1149.1), On-chip scan compression...
Updated:
2012-Aug-16 09:53 AM
By: CambioRole: DFT Engineer
Experience Level: 3.0 to 10.0 yrsLocation: Bangalore (India)
Employer:
Cambio Consulting India Pvt Ltd
Critical Requirements For Synthesis Engineerfor Top Semiconductor Companies
Job functions include: Synthesis optimization to maximize power and performance. Development of Synopsys Design Constraints (SDC) to capture timing goals and signoff criteria. In-depth, hands-on understanding of the ASIC design flow to tapeout including all aspects of Floorplanning, Synthesis,...
Updated:
2012-May-22 11:28 AM
By: CambioIndustry: HardwareRole: Technical Lead
Experience Level: 8.0 to 12.0 yrsLocation: Not Specified (India)
Employer:
Cambio Consulting India Pvt Ltd
Custom Layout / Memory Layout / IO Layout Jobs @ Malaysia
Onsite opportunity for Layout Engineers @ Malaysia Role : Layout Design Engineer (Custom Layout / Library Development / IO Layout) Qualification : B.E/B.Tech /M.Tech/ M.S/ M.E in Electrical or Electronics Engg Experience : 3 -8 Years Location : Malaysia (Valid passport is mandatory)
Updated:
2013-May-11 07:13 AM
By: Roland and AssociatesIndustry: SemiconductorRole: Layout Engineer
Experience Level: 3.0 to 8.0 yrsLocation: Malaysia (Malaysia)
Vacancy Physical Design Experts onsite
Vacancy Physical Design Experts onsite
Updated:
2013-May-08 06:09 AM
By: Roland and AssociatesIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 7.0 to 8.0 yrsLocation: Malaysia (Malaysia)
Vacancy Physical design Engineer onsite
Vacancy Physical design Engineer onsite
Updated:
2013-May-08 06:09 AM
By: Roland and AssociatesIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 7.0 to 8.0 yrsLocation: Malaysia (Malaysia)
Vacancy SoC Encounter Users onsite
Vacancy SoC Encounter Users onsite
Updated:
2013-May-08 06:09 AM
By: Roland and AssociatesIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 7.0 to 8.0 yrsLocation: Malaysia (Malaysia)
Vacancy Magma talus Users onsite
Vacancy Magma talus Users onsite
Updated:
2013-May-08 06:09 AM
By: Roland and AssociatesIndustry: SemiconductorRole: Physical Design Engineer
Experience Level: 7.0 to 8.0 yrsLocation: Malaysia (Malaysia)
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