can any one explain wat is ment by Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Packet Transform ??

Hi there, by exploiting the in-place nature of the DWPT algorithm, the architecture has an efficient pipeline structure to implement high-throughput processing. Folded architecture for lifting-based wavelet filters is proposed to compute wavelet butterflies in different groups simultaneously, at each decomposition level. Internal pipelining and by pass mode are employed on each processing element to increase computation throughput and provide easy configuration for arbitrary decomposition, respectively. According to the comparison results, the proposed VLSI architecture is more efficient than previous proposed architectures in terms of arithmetic operations, storage requirement, and throughput.

Hope this helps Ramesh.