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Hardware Designers (VLSI)

 
Asked by : Deepa Sawant, Project Manager, Motorola
Industry : Hardware
Functional Area : Business Policy
Activity: Question posted: 04 24 2008 22:37:55 +0000, 2 answers, 6546 views, last activity 07 06 2010 20:18:08 +0000
 
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  Answered by     Ramesh.M , Hardware Design Engineer, Micron Technology  | 02 09 2009 11:26:16 +0000
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Simulation is used to verify the functionality of the circuit.. a)Functional Simulation:study of ckt's operation independent of timing parameters and gate delays. b) Timing Simulation :study including estimated delays, verify setup,hold and other timing requirements of devices like flip flops are met.

Synthesis:One of the foremost in back end steps where by synthesizing is nothing but converting VHDL or VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology.Basically the synthesis tools convert the design description into equations or components

  Answered by     Sonal Singh, Project Manager, Nortel Networks  | 04 24 2008 22:38:20 +0000
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Simulation <= verify your design.
synthesis <= Check for your timing


Simulation is used to verify the functionality of the circuit.. a)Functional Simulation:study of ckt's operation independent of timing parameters and gate delays. b) Timing Simulation :study including estimated delays, verify setup,hold and other timing requirements of devices like flip flops are met.
Synthesis:One of the foremost in back end steps where by synthesizing is nothing but converting VHDL or VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology.Basically the synthesis tools convert the design description into equations or components

 
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